A Framework for Asip and Multiprocessor Architectures Integration within Reconfigurable Soc and Fpga Devices

Δ˰λϼΨϟ΍ : ΖΒδΘϛ΍ ΪϘϟ ΓΩΪΤϣ ΕΎϘϴΒτΗ ϲϓ ΔμΘΨϤϟ΍ ΕΎΠϟΎόϤϟ΍ (ASIPs) ϲϓ ΔϴΒόη ϝΎΠϣ ΝΎΘϧ· ϟ΍ ϖ΋Ύϗή ϥ΄θϟ΍ Ϯϫ ΎϤϛ ϲϓ ρΎγϭϷ΍ ΔϴΜΤΒϟ΍. ϓ ϲϬ (ASIPs) ˱ ϼΣ ήϓϮΗ ˱ ΎόΟΎϧ ˱ ΎϘϓϮϣ ϦϴΑ Γ˯ΎϔϜϟ΍ ΔϧϭήϤϟ΍ϭ ΔΠϣΪϤϟ΍ ΔϤψϧϸϟ ΔΒδϨϟΎΑ ASIP ΪόΘϣ ήΧ΁ ϭ Ω ΠϟΎόϤϟ΍ ΕΎ. 4 ABSTRACT Application-Specific Instruction-set Processors (ASIPs) have gained popularity in production chips as well as in the research community. They offer a viable solution to the tradeoff between efficiency and flexibility for the embedded System-on-a-Chip (SoC). Generally, an ASIP has the capability to extend the base instruction set of a general-purpose processor with a set of customized instructions supported by the specific hardware resources provided on the ASIP. The hardware implementing the specific instructions can be either runtime reconfigurable functional units, or pre-synthesized circuits. In this paper, we propose a framework for prototype application within FPGAs devices using ASIPs and multiprocessors architecture. Firstly, we provide an overview of a method to identify coarse and finite grain instruction set extensions in application code and integration process of ASIP. Second, we split the data input application to get concurrence and the data dependency of the target application in order to process to multiprocessor execution. Finally, we compare the performances levels given by the execution of the application using ASIP architecture and multiprocessor architecture.